1. Field of Invention
The invention relates to a 3-D stackable semiconductor package, and more particularly to a 3-D stackable semiconductor package combining two components back to back.
2. Related Art
Although the electronic packaging is often seen to be a minor technology of manufacturing semiconductors, it determines the size and the cost of the electronic products, and therefore its importance should not be underestimated.
Electronic packaging includes single chip packaging (SCP) and multi-chip packaging (MCP). MCP includes a multi-chip module (MCM). The MCP, also called 3-D stackable packaging, has became the mainstream of electronic packaging, for it satisfies the demands for small, cheap, and multi-functional electronic products, and therefore lowers the cost and simplifies the process of the MCP.
U.S. Pat. No. 6,359,340 discloses a multi-chip module having a stacked chip arrangement. It stacks chips on a substrate and electrically connects to each chip by wire bonding technology. Although the developed wire bonding lowers the cost, it increases the size of the module.
U.S. Pat. No. 6,611,052 discloses a wafer level stackable semiconductor package. It stacks each chip on a substrate with electric conductive bumps disposed on the surface of the chips to form electric connection. Since this semiconductor package can perform electric tests only after stacking all chips, the whole package is useless if any single chip is disabled.